1. Field of the Invention
The present invention relates to fabricating semiconductor devices and more particularly to forming low capacitance interconnect structures for semiconductor devices.
2. Description of Previous Art
As advances in processing technology allow ever increasing numbers of integrated devices to be fabricated on a single integrated circuit (IC), the device geometries of the integrated devices are fabricated at ever decreasing scales. The sizes of the individual integrated devices get progressively smaller. At these reduced device geometries, the ability of the devices to store electrical energy is also reduced. Thus, as the size of the devices get smaller, the capacitance at source and drain junctions and gates of the individual devices is reduced. The total capacitances of individual devices on ICs are also reduced.
At these reduced device capacitance levels, the capacitances of interconnect lines that couple the devices contribute much of the total capacitance associated with each device node. The interconnect capacitance becomes a significant fraction of the capacitance on each circuit node. Particularly, in high speed circuits, interconnect capacitances limit the speeds at which the circuits can function. The problem is even more pronounced in today's reduced device geometry designs. Interconnects on advanced IC's are more dense and more abundant in order to accommodate the increased number of signals in these advanced products. Thus, as the need for smaller, faster, and more complex circuits increases, interconnect capacitance becomes a major problem. The interconnect capacitance problem must be addressed in order to ensure the proper operation of these advanced circuits.
The capacitance of an interconnect line increases with the length of the interconnect line and with the proximity of the interconnect line to other conductors. Stated differently, the interconnect capacitance is proportional to the length of the line and is inversely proportional to the spacing between the line and other conductors. The materials surrounding an interconnect line also affect the capacitances between the line and other proximate conductors. Materials with high dielectric constants increase the interconnect line capacitance, while materials with low dielectric constants decrease the interconnect line capacitance. Stated differently, the dielectric constants of the materials surrounding an interconnect are proportional to the capacitance of the interconnect line. By carefully choosing the type of materials that will surround the interconnect lines of an integrated circuit, the capacitance of the interconnect lines can be manipulated.
Currently, the dielectric constants of materials that are in use for surrounding interconnect lines have relatively high dielectric constants. Some examples of these materials are silicon with a relative dielectric constant of approximately 11.7, silicon nitride with a relative dielectric constant of approximately 7.0, silicon oxide with a relative dielectric constant of approximately 3.9, spin-on glass with a relative dielectric constant of approximately 7.0, and plasma oxynitride or oxide with a relative dielectric constant in the range of approximately 4.0 to 7.0. The exact value of the relative dielectric constant of a region of plasma oxynitride or of a region of plasma oxide depends upon the particular composition of the region. The dielectric constants of these materials and others currently in use are high and cause capacitance problems for integrated circuits fabricated with reduced geometries.
Also, the speed at which these reduced geometry integrated circuits can operate is limited. Advantages in miniaturizing IC's cannot be fully realized when high interconnect capacitance between the devices impose speed limitations on the operation speed of the IC's. As IC fabrication technology develops and produces smaller, faster, and denser IC's, the increased complexity of the interconnects between the integrated devices will further underscore the importance of reducing interconnect capacitance of integrated circuits.
Therefore, it is desirable to provide a method of forming interconnect lines for integrated circuits with low conductor line capacitance between the devices on the integrated circuit. Smaller, faster, and more complex, and more densely packed devices contribute greater advantages to higher performing IC's when interconnect lines have low conductor line capacitance.